In the field of semiconductor, the super PN junction technique used to improve the performance of power MOS has become significantly prominent in high-voltage applications.
The conventional fabrication process of super PN junctions mainly includes deep trench etching, epitaxial filling, and silicon CMP planarizing.
Specifically, the conventional fabrication process of a super PN junction includes following steps:
Step 1: forming a single thick epitaxial layer (N type) on an N+ silicon substrate;
Step 2: forming deep trenches in the epitaxial layer. Specifically, first forming a thermal oxide layer, then depositing a silicon nitride layer, then depositing a plasma enhanced chemical vapor deposition oxide layer, by etching the above mentioned three layers to the silicon substrate, then removing the photoresist, and use the above mentioned three layers as a hard mask to do a etching process to form deep trenches, then removing the plasma enhanced chemical vapor deposition oxide layer using a wet etching method.
Step 3: forming super PN junctions by filling the deep trenches with epitaxial silicon (P type).
Step 4: planarizing the surface of the silicon substrate using a CMP process.
However, with respect to the CMP process used herein, because equipment for the CMP process is usually used in the back-end-of-line processing, they cannot be shared with the fabrication process of a super PN junction. Therefore the conventional fabrication process of a super junction utilizing the CMP process to obtain planarization often needs dedicated CMP equipment, which causes difficult process control and increased production cost.